View ADE7755ARSZ_6386622.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

energy metering ic with pulse output ade7755 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2002C2009 analog devices, inc. all rights reserved. features high accuracy, surpasses 50 hz/60 hz iec 687/iec 1036 less than 0.1% error over a dynamic range of 500 to 1 supplies active power on the frequency outputs, f1 and f2 high frequency output cf is intended for calibration and supplies instantaneous active power synchronous cf and f1/f2 outputs logic output revp provides information regarding the sign of the active power direct drive for electromechanical counters and 2-phase stepper motors (f1 and f2) programmable gain amplifier (pga) in the current channel facilitates usage of small shunts and burden resistors proprietary adcs and dsps provide high accuracy over large variations in environmental conditions and time on-chip power supply monitoring on-chip creep protection (no load threshold) on-chip reference 2.5 v 8% (30 ppm/c typical) with external overdrive capability single 5 v supply, low power (15 mw typical) low cost cmos process general description the ade7755 is a high accuracy electrical energy measurement ic. the part specifications surpass the accuracy requirements as quoted in the iec 1036 standard. the only analog circuitry used in the ade7755 is in the adcs and reference circuit. all other signal processing (for example, multiplication and filtering) is carried out in the digital domain. this approach provides superior stability and accuracy over extremes in environmental conditions and over time. the ade7755 supplies average active power information on the low frequency outputs, f1 and f2. these logic outputs can be used to directly drive an electromechanical counter or interface to an mcu. the cf logic output gives instantaneous active power information. this output is intended to be used for calibration purposes or for interfacing to an mcu. the ade7755 includes a power supply monitoring circuit on the av dd supply pin. the ade7755 remains in a reset condition until the supply voltage on av dd reaches 4 v. if the supply falls below 4 v, the ade7755 resets and no pulse is issued on f1, f2, and cf. internal phase matching circuitry ensures that the voltage and current channels are phase matched whether the hpf in channel 1 is on or off. an internal no load threshold ensures that the ade7755 does not exhibit any creep when there is no load. the ade7755 is available in a 24-lead ssop package. functional block diagram power supply monitor g0 g1 av dd agnd dv dd dgnd reset f2 f1 cf revp s1s0 scf clkout clkin ref in/out ade7755 4k? 2.5v reference adc pga 1, 2, 8, 16 v1p v1n v2p v2n digital-to-frequency converter ...110101... ...11011001... adc 23 9 24 22 20 13 14 12 18 17 10 21 1 2 11 3 15 16 dc ac/ 5 6 8 7 02896-001 phase correction lpf hpf signal processing block multiplier figure 1. 1 u.s. patents 5,745,323; 5,760,617; 5,862,069; and 5,872,469.
ade7755 rev. a | page 2 of 20 table of contents features .............................................................................................. 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? timing characteristics ................................................................ 4 ? absolute maximum ratings ............................................................ 5 ? esd caution .................................................................................. 5 ? pin configuration and function descriptions ............................. 6 ? typical performance characteristics ............................................. 8 ? terminology .................................................................................... 11 ? theory of operation ...................................................................... 12 ? power factor considerations .................................................... 12 ? nonsinusoidal voltage and current ........................................ 13 ? analog inputs ............................................................................. 13 ? typical connection diagrams .................................................. 14 ? power supply monitor ............................................................... 14 ? digital-to-frequency conversion ............................................ 15 ? interfacing the ade7755 to a microcontroller for energy measurement ............................................................................... 16 ? power measurement considerations ....................................... 16 ? transfer function ....................................................................... 17 ? selecting a frequency for an energy meter application ...... 18 ? frequency outputs ..................................................................... 18 ? no load threshold .................................................................... 19 ? outline dimensions ....................................................................... 20 ? ordering guide .......................................................................... 20 ? revision history 8/09rev. 0 to rev. a changes to format ............................................................. universal changes to features section and general description section . 1 moved figure 2 ................................................................................. 4 changes to pin 22, pin 23, and pin 24 descriptions, table 4 ..... 7 changes to terminology section.................................................. 11 changes to theory of operation section, figure 22, power factor considerations section, and figure 23 ............................ 12 changes to nonsinusoidal voltage and current section and analog inputs section .................................................................... 13 changes to figure 27 ...................................................................... 14 changes to hpf and offset effects section, figure 29, and digital-to-frequency conversion section .................................. 15 changes to figure 32 ...................................................................... 16 changes to transfer function section ......................................... 17 changes to selecting a frequency for an energy meter application section ........................................................................ 18 changes to no load threshold section ...................................... 19 updated outline dimensions ....................................................... 20 changes to ordering guide .......................................................... 20 5/02revision 0: initial version
ade7755 rev. a | page 3 of 20 specifications av dd = dv dd = 5 v 5%, agnd = dgnd = 0 v, on-chip reference, clkin = 3.58 mhz, t min to t max = ?40c to +85c. table 1. parameter min typ max unit test conditions/comments accuracy 1 , 2 measurement error 1 on channel 1 channel 2 with full-scale signal (660 mv), 25c gain = 1 0.1 % reading over a dynamic range of 500 to 1 gain = 2 0.1 % reading over a dynamic range of 500 to 1 gain = 8 0.1 % reading over a dynamic range of 500 to 1 gain = 16 0.1 % reading over a dynamic range of 500 to 1 phase error 1 between channels line frequency = 45 hz to 65 hz v1 phase lead 37 (pf = 0.8 capacitive) 0.1 degrees ac/ dc = 0 and ac/ dc = 1 v1 phase lag 60 (pf = 0.5 inductive) 0.1 degrees ac/ dc = 0 and ac/ dc = 1 ac power supply rejection 1 ac/ dc = 1, s0 = s1 = 1, g0 = g1 = 0 output frequency variation (cf) 0.2 % reading v1 = 100 mv rms, v2 = 100 mv rms @ 50 hz, ripple on av dd of 200 mv rms @ 100 hz dc power supply rejection 1 ac/ dc = 1, s0 = s1 = 1, g0 = g1 = 0 output frequency variation (cf) 0.3 % reading v1 = 100 mv rms, v2 = 100 mv rms, av dd = dv dd = 5 v 250 mv analog inputs see the analog inputs section maximum signal levels 1 v v1p, v1n, v2n, and v2p to agnd input impedance (dc) 390 k clkin = 3.58 mhz ?3 db bandwidth 14 khz clkin/256, clkin = 3.58 mhz adc offset error 1 , 2 25 mv gain = 1 1 , 2 gain error 1 7 % ideal external 2.5 v reference, gain = 1 v1 = 470 mv dc, v2 = 660 mv dc gain error match 1 0.2 % ideal external 2.5 v reference reference input ref in/out input voltage range 2.7 v 2.5 v + 8% 2.3 v 2.5 v ? 8% input impedance 3.2 k input capacitance 10 pf on-chip reference nominal 2.5 v reference error 200 mv temperature coefficient 30 ppm/c clkin note all specifications for clkin of 3.58 mhz input clock frequency 4 mhz 1 mhz logic inputs 3 scf, s0, s1, ac/ dc , reset , g0, and g1 input high voltage, v inh 2.4 v dv dd = 5 v 5% input low voltage, v inl 0.8 v dv dd = 5 v 5% input current, i in 3 a typically 10 na, v in = 0 v to dv dd input capacitance, c in 10 pf logic outputs 3 f1 and f2 output high voltage, v oh 4.5 v i source = 10 ma, dv dd = 5 v output low voltage, v ol 0.5 v i sink = 10 ma, dv dd = 5 v cf and revp output high voltage, v oh 4 v i source = 5 ma, dv dd = 5 v output low voltage, v ol 0.5 v i sink = 5 ma, dv dd = 5 v
ade7755 rev. a | page 4 of 20 parameter min typ max unit test conditions/comments power supply for specified performance av dd 4.75 v 5 v ? 5% 5.25 v 5 v + 5% dv dd 4.75 v 5 v ? 5% 5.25 v 5 v + 5% ai dd 3 ma typically 2 ma di dd 2.5 ma typically 1.5 ma 1 see the terminology section. 2 see the typical performance characteristics section for the plots. 3 sample tested during initial releas e and after any redesign or process change that may affect this parameter. timing characteristics av dd = dv dd = 5 v 5%, agnd = dgnd = 0 v, on-chip reference, clkin = 3.58 mhz, t min to t max = ?40c to +85c. table 2. parameter 1 , 2 specification unit test conditions/comments t 1 3 275 ms f1 and f2 pulse width (logic low) t 2 see table 7 sec output pulse period; see the transfer function section t 3 1/2 t 2 sec time between f1 falling edge and f2 falling edge t 4 3 , 4 90 ms cf pulse width (logic high) t 5 see table 8 sec cf pulse period; see the transfer function section t 6 clkin/4 sec minimum time between f1 and f2 pulse 1 sample tested during initial releas e and after any redesign or process change that may affect this parameter. 2 see figure 2. 3 the pulse widths of f1, f2, and cf ar e not fixed for higher output frequencies. see the frequency outputs section. 4 the cf pulse is always 18 s in the high frequency mode. see the frequency outputs section and table 8. f1 f2 cf t 1 t 5 t 4 t 2 t 6 t 3 0 2896-002 figure 2. timing diagram for frequency outputs
ade7755 rev. a | page 5 of 20 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rating av dd to agnd ?0.3 v to +7 v dv dd to dgnd ?0.3 v to +7 v dv dd to av dd ?0.3 v to +0.3 v analog input voltage to agnd v1p, v1n, v2p, and v2n ?6 v to +6 v reference input voltage to agnd ?0.3 v to av dd + 0.3 v digital input voltage to dgnd ?0.3 v to dv dd + 0.3 v digital output voltage to dgnd ?0.3 v to dv dd + 0.3 v operating temperature range industrial ?40c to +85c storage temperature range ?65c to +150c junction temperature 150c 24-lead ssop, power dissipation 450 mw ja thermal impedance 112c/w lead temperature, soldering vapor phase (60 sec) 215c infrared (15 sec) 220c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ade7755 rev. a | page 6 of 20 pin configuration and fu nction descriptions dv dd 1 ac/dc 2 av dd 3 nc 4 f1 24 f2 23 cf 22 dgnd 21 v1p 5 v1n 6 v2n 7 revp 20 nc 19 clkout 18 v2p 8 clkin 17 reset 9 g0 16 ref in/out 10 g1 15 agnd 11 s0 14 scf 12 s1 13 nc = no connect ade7755 top view (not to scale) 02896-003 figure 3. pin configuration table 4. pin function descriptions pin o. mnemonic description 1 dv dd digital power supply. this pin provides the supply voltag e for the digital circuitry in the ade7755. the supply voltage should be maintained at 5 v 5% for specified operation. this pin should be decoupled with a 10 f capacitor in parallel with a ceramic 100 nf capacitor. 2 ac/ dc high-pass filter select. this logic input is used to en able the hpf in channel 1 (current channel). a logic 1 on this pin enables the hpf. the associated phase response of this filter is internally compensated over a frequency range of 45 hz to 1 khz. the hpf should be enabled in power metering applications. 3 av dd analog power supply. this pin provides the supply voltag e for the analog circuitry in the ade7755. the supply should be maintained at 5 v 5% for specified operation. every effort should be made to minimize power supply ripple and noise at this pin by the use of proper decoupling. this pin should be decoupled to agnd with a 10 f capacitor in parallel with a ceramic 100 nf capacitor. 4, 19 nc no connect. 5, 6 v1p, v1n analog inputs for channel 1 (current channel). these in puts are fully differential voltage inputs with a maximum differential signal level of 470 mv for specif ied operation. channel 1 also has a pga, and the gain selections are outlined in table 5 . the maximum signal level at these pins is 1 v with respect to agnd. both inputs have internal esd protection circuitry. an overvo ltage of 6 v can be sustained on these inputs without risk of permanent damage. 7, 8 v2n, v2p negative and positive inputs for channe l 2 (voltage channel). these inputs pr ovide a fully differential input pair with a maximum differential input voltage of 660 mv for specified operation. the maximum signal level at these pins is 1 v with respect to ag nd. both inputs have internal esd prot ection circuitry, and an overvoltage of 6 v can be sustained on these inp uts without risk of permanent damage. 9 reset reset pin. a logic low on this pin holds the adcs and digital circuitry in a reset condition. bringing this pin logic low clears the ade7755 internal registers. 10 ref in/out this pin provides access to the on-chip voltage reference. the on-chip reference has a nominal value of 2.5 v 8% and a typical temperature coefficient of 30 ppm/c. an external reference source may also be connected at this pin. in either case, this pin should be decoupled to agnd with a 1 f ceramic capacitor and a 100 nf ceramic capacitor. 11 agnd this pin provides the ground reference for the analog ci rcuitry in the ade7755, that is, the adcs and reference. this pin should be tied to the analog ground plane of the pcb. the analog ground plane is the ground reference for all analog circuitry, for example, antialiasing filters and current and voltage transducers. for good noise suppression, the analog ground plane should be connected to the digital ground plane at one point only. a star ground configuration helps to keep noisy di gital currents away from the analog circuits. 12 scf select calibration frequency. this logic input is used to select the frequency on the calibration output, cf. table 8 shows how the calibration frequencies are selected. 13, 14 s1, s0 these logic inputs are used to select one of four possible frequencies for the digital-to-frequency conversion. this offers the designer greater flexibility when designing the energy meter. see the selecting a frequency for an energy meter application section. 15, 16 g1, g0 these logic inputs are used to select one of four possi ble gains for channel 1, that is, v1. the possible gains are 1, 2, 8, and 16. see the analog inputs section.
ade7755 rev. a | page 7 of 20 pin no. mnemonic description 17 clkin an external clock can be provided at this logic input. alternatively, a parallel resonant at crystal can be connected across clkin and clkout to provide a clock source for the ade7755. the clock frequency for specified operation is 3.579545 mhz. crystal load capaci tance of between 22 pf and 33 pf (ceramic) should be used with the gate oscillator circuit. 18 clkout a crystal can be connected across this pin and clkin to provide a clock source for the ade7755. the clkout pin can drive one cmos load when an external clock is supplied at clkin or by the gate oscillator circuit. 20 revp this logic output goes logic high when negative power is detected, that is, when the phase angle between the voltage and current signals is greater than 90. this o utput is not latched and is reset when positive power is detected again. the output goes high or low at the same time that a pulse is issued on cf. 21 dgnd this pin provides the ground reference for digital circui try in the ade7755, that is, the multiplier, filters, and digital-to-frequency converter. this pin should be tied to the digital ground plane of the pcb. the digital ground plane is the ground reference for all digital circuitry, for example, counters (mechanical and digital), mcus, and indicator leds. for good noise suppression, the analog ground plane should be conne cted to the digital ground plane at one point only, for example, a star ground. 22 cf calibration frequency logic output. the cf logic output gives instantaneous active power information. this output is intended to be used for calibrat ion purposes. also, see the scf pin description. 23, 24 f2, f1 low frequency logic outputs. f1 and f2 supply averag e active power information. the logic outputs can be used to directly drive electromechanical counters and 2-phase stepper motors. see the transfer function section.
ade7755 rev. a | page 8 of 20 typical performance characteristics 0.1 0.01 1 10 0.5 0.4 0.3 0.2 error (%) full-scale current (%) ?40c +25c +85c pf = 1 gain = 1 on-chip reference 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 ?0.5 100 02896-004 0.1 0.01 1 10 0.5 0.4 0.3 0.2 error (%) full-scale current (%) 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 ?0.5 100 ?40c +25c +85c pf = 1 gain = 16 on-chip reference 02896-007 figure 4. error as a % of reading (gain = 1) figure 7. error as a % of reading (gain = 16) 0.1 0.01 1 10 0.5 0.4 0.3 0.2 error (%) full-scale current (%) 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 ?0.5 100 ?40c +25c +85c pf = 1 gain = 2 on-chip reference 02896-005 0.1 0.01 1 10 0.6 0.4 0.2 0 error (%) full-scale current (%) ?0.2 ?0.4 ?0.6 100 pf = 0.5 gain = 1 on-chip reference ?40c pf = 0.5 +25c pf = 1 +25c pf = 0.5 +85c pf = 0.5 02896-008 figure 5. error as a % of reading (gain = 2) figure 8. error as a % of reading (gain = 1) 0.1 0.01 1 10 0.6 0.4 0.2 0 error (%) full-scale current (%) ?0.2 ?0.4 ?0.6 100 pf = 0.5 gain = 2 on-chip reference ?40c pf = 0.5 +25c pf = 1 +25c pf = 0.5 +85c pf = 0.5 02896-009 0.1 0.01 1 10 0.6 ?40c pf = 1 gain = 8 on-chip reference +25c +85c 0.5 0.4 0.3 error (%) full-scale current (%) 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 100 02896-006 figure 6. error as a % of reading (gain = 8) figure 9. error as a % of reading (gain = 2)
ade7755 rev. a | page 9 of 20 0.1 0.01 1 10 0.8 0.6 0.4 0.2 error (%) full-scale current (%) ?0.2 ?0.6 ?0.4 0 ?0.8 100 pf = 0.5 gain = 8 on-chip reference ?40c pf = 0.5 +25c pf = 1 +25c pf = 0.5 +85c pf = 0.5 02896-010 figure 10. error as a % of reading (gain = 8) 0.1 0.01 1 10 0.4 0.2 0 ?0.2 error (%) full-scale current (%) ?0.6 ?0.8 ?0.4 ?1.0 100 ?40c pf = 0.5 +25c pf = 1 +25c pf = 0.5 +85c pf = 0.5 pf = 0.5 gain = 16 on-chip reference 0 2896-011 figure 11. error as a % of reading (gain = 16) 0.1 0.01 1 10 error (%) full-scale current (%) 100 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 pf = 1 gain = 2 external reference +25c ?40c +85c 02896-012 figure 12. error as a % of reading over temperature with an external reference (gain = 2) 0.1 0.01 1 10 error (%) full-scale current (%) 100 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 pf = 1 gain = 16 external reference ?40c +25c +85c 02896-013 figure 13. error as a % of reading over temperature with an external reference (gain = 16) 50 45 60 55 70 65 0.8 0.6 0.4 0.2 error (%) frequency (hz) 0 ?0.2 ?0.4 ?0.6 75 pf = 1 pf = 0.5 02896-014 figure 14. error as a % of reading over frequency 40a to 40ma 500 ? 1.5m ? 10m ? 1k? 1m ? 1k? 10f 100nf nc av dd ac/dc dv dd f1 f2 u1 ade7755 cf revp nc clkout clkin g0 g1 s0 s1 scf v1p v1n v2n v2p ref in/out 100nf 10f k7 nc = no connect ps2501-1 33pf 33pf k8 10k? 10nf 10nf 10nf v dd reset agnd dgnd y1 3.58mhz gain select u3 v dd v dd 33nf 33nf 100nf 33nf 1k ? 10f 220v 33nf 1k? 4 321 24 1 4 3 2 23 22 20 19 18 17 16 15 14 13 12 21 11 9 5 6 7 8 10 02896-015 figure 15. test circuit for performance curves
ade7755 rev. a | page 10 of 20 ?9 ?3 ?15 3 9 16 14 12 10 8 6 4 2 0 15 gain = 1 temperature = 25c distribution characteristics number points: 101 minimum: ?9.78871 maximum: 7.2939 mean: ?1.73203 std. dev: 3.61157 02896-016 hits ch1 offset (mv) ?9 ?3 ?15 3 9 30 25 20 15 10 5 0 15 gain = 8 temperature = 25c distribution characteristics number points: 101 minimum: ?2.48959 maximum: 5.81126 mean: ?1.26847 std. dev: 1.57404 02896-019 hits ch1 offset (mv) figure 16. channel 1 offset distribution (gain = 1) figure 19. channel 1 offset distribution (gain = 8) ?9 ?3 ?15 3 9 18 14 16 12 10 8 6 4 2 0 15 gain = 2 temperature = 25c distribution characteristics number points: 101 minimum: ?5.61779 maximum: 6.40821 mean: ?0.01746 std. dev: 2.35129 02896-017 hits ch1 offset (mv) ?9 ?3 ?15 3 9 35 30 25 20 10 15 5 0 15 gain = 16 temperature = 25c distribution characteristics number points: 101 minimum: ?1.96823 maximum: 5.71177 mean: ?1.48279 std. dev: 1.47802 02896-020 hits ch1 offset (mv) figure 17. channel 1 offset distribution (gain = 2) figure 20. channel 1 offset distribution (gain = 16) 0.1 0.01 1 10 0.5 0.4 0.3 0.2 error (%) full-scale current (%) 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 ?0.5 ?0.6 100 5v 4.75v 5.25v 02896-018 0.1 0.01 1 10 0.5 0.4 0.3 0.2 error (%) full-scale current (%) 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 ?0.5 ?0.6 100 4.75v 5.25v 5v 02896-021 figure 18. psr with internal reference (gain = 16) figure 21. psr with extern al reference (gain = 16)
ade7755 rev. a | page 11 of 20 terminology measurement error the error associated with the energy measurement made by the ade7755 is defined by the following formula: %100 7755 ? = energytrue energytrue adetheby registered energy erro r percentage phase error between channels the high-pass filter (hpf) in channel 1 has a phase lead response. to offset this phase response and equalize the phase response between channels, a phase compensation network is also placed in channel 1. the phase compensation network matches the phase to within 0.1 over a range of 45 hz to 65 hz and 0.2 over a range of 40 hz to 1 khz. see figure 30 and figure 31 . power supply rejection (psr) the psr quantifies the ade7755 measurement error as a percentage of the reading when the power supplies are varied. for the ac psr measurement, a reading at nominal supplies (5 v) is taken. a 200 mv rms/100 hz signal is then introduced onto the supplies and a second reading is obtained under the same input signal levels. any error introduced is expressed as a percentage of the reading (see the measurement error definition). for the dc psr measurement, a reading at nominal supplies (5 v) is taken. the supplies are then varied 5% and a second reading is obtained with the same input signal levels. any error introduced is again expressed as a percentage of the reading. adc offset error the adc offset error refers to the dc offset associated with the analog inputs to the adcs. it means that with the analog inputs connected to agnd, the adcs still see a small dc signal (offset). the offset decreases with increasing gain in channel 1. this specification is measured at a gain of 1. at a gain of 16, the dc offset is typically less than 1 mv. however, when the hpf is switched on, the offset is removed from the current channel, and the power calculation is not affected by this offset. gain error the gain error of the ade7755 is defined as the difference between the measured output frequency (minus the offset) and the ideal output frequency. it is measured with a gain of 1 in channel 1. the difference is expressed as a percentage of the ideal frequency. the ideal frequency is obtained from the ade7755 transfer function (see the transfer function section). gain error match the gain error match is defined as the gain error (minus the offset) obtained when switching between a gain of 1 and a gain of 2, 8, or 16. it is expressed as a percentage of the output frequency obtained under a gain of 1. this gives the gain error observed when the gain selection is changed from 1 to 2, 8, or 16.
ade7755 rev. a | page 12 of 20 theory of operation the two adcs of the ade7755 digitize the voltage signals from the current and voltage transducers. these adcs are 16-bit, second-order - with an oversampling rate of 900 khz. this analog input structure greatly simplifies transducer interfacing by providing a wide dynamic range for direct connection to the transducer and also by simplifying the antialiasing filter design. a programmable gain stage in the current channel further facilitates easy transducer interfacing. a high-pass filter in the current channel removes any dc components from the current signal. this removal eliminates any inaccuracies in the active power calculation due to offsets in the voltage or current signals (see the hpf and offset effects section). the active power calculation is derived from the instantaneous power signal. the instantaneous power signal is generated by a direct multiplication of the current and voltage signals. to extract the active power component (that is, the dc component), the instantaneous power signal is low-pass filtered. figure 22 illustrates the instantaneous active power signal and shows how the active power information can be extracted by low-pass filtering the instantaneous power signal. this scheme correctly calculates active power for nonsinusoidal current and voltage waveforms at all power factors. all signal processing is carried out in the digital domain for superior stability over temperature and time. time adc pga adc ch1 ch2 multiplier f1 f2 digital-to- frequency cf digital-to- frequency instantaneous active power signal instantaneous power signal {p(t)} lpf hpf v i 2 v i 2 v i p(t) = i(t) v(t) where: v(t) = v cos( t) i(t) = i cos( t) p(t) = v i {1+cos (2 t)} 2 0 2896-022 figure 22. signal processing block diagram the low frequency output of the ade7755 is generated by accumulating this active power information. this low frequency inherently means a long accumulation time between output pulses. the output frequency is therefore proportional to the average active power. this average active power information can, in turn, be accumulated (for example, by a counter) to generate active energy information. because of its high output frequency and shorter integration time, the calibration frequency (cf) output is proportional to the instantaneous active power. this is useful for system calibration purposes that take place under steady load conditions. power factor considerations the method used to extract the active power information from the instantaneous power signal (that is, by low-pass filtering) is valid even when the voltage and current signals are not in phase. figure 23 displays the unity power factor condition and a displacement power factor (dpf) = 0.5, that is, current signal lagging the voltage by 60. assuming that the voltage and current waveforms are sinusoidal, the active power component of the instantaneous power signal (that is, the dc term) is given by qu u 60cos 2 iv this is the correct active power calculation. v i 2 0v current voltage voltage current v i 2 cos(60) 0v inst a nt a neous power signal instantaneous a ctive power signal instantaneous power signal instantaneous active power signal 60 0 2896-023 figure 23. dc component of instantaneous power signal conveys active power information pf < 1
ade7755 rev. a | page 13 of 20 nonsinusoidal voltage and current the active power calculation method also holds true for non- sinusoidal current and voltage waveforms. all voltage and current waveforms in practical applications have some harmonic content. using the fourier transform operation, instantaneous voltage and current waveforms can be expressed in terms of their harmonic content. ( ++= 0 tsin 2)( h h h o a h v vtv ) (1) where: v(t) is the instantaneous voltage. v o is the average voltage value. v h is the rms value of the voltage harmonic, h. a h is the phase angle of the voltage harmonic. ++= 0 )tsin( 2)( h h h o h i iti (2) where: i(t) is the instantaneous current. i o is the current dc component. i h is the rms value of the current harmonic, h. h is the phase angle of the current harmonic. using equation 1 and equation 2, the active power (p ) can be expressed in terms of its fundamental active power (p1) and harmonic active power (p h ). p = p 1 + p h (3) where: p 1 is the active power of the fundamental component: p 1 = v 1 i 1 cos 1 1 = 1 C 1 and p h is the active power of all harmonic components: ?= 1 cos h hhh h ivp h = h C h a harmonic active power component is generated for every harmonic, provided that the harmonic is present in both the voltage and current waveforms. the power factor calculation previously shown is accurate in the case of a pure sinusoid; therefore, the harmonic active power must also correctly account for the power factor because it is made up of a series of pure sinusoids. note that the input bandwidth of the analog inputs is 14 khz with a master clock frequency of 3.5795 mhz. analog inputs channel 1 (current channel) the voltage output from the current transducer is connected to the ade7755 at channel 1. channel 1 is a fully differential voltage input. v1p is the positive input with respect to v1n. the maximum peak differential signal on channel 1 should be less than 470 mv (330 mv rms for a pure sinusoidal signal) for specified operation. note that channel 1 has a programmable gain amplifier (pga) with user-selectable gain of 1, 2, 8, or 16 (see table 5 ). these gains facilitate easy transducer interfacing. +470m v ? 470m v v cm v 1 differential input 470mv max peak common-mode 100mv max v1p v1n v1 v cm agnd 02896-024 figure 24. maximum signal levels, channel 1, gain = 1 figure 24 illustrates the maximum signal levels on v1p and v1n. the maximum differential voltage is 470 mv divided by the gain selection. the differential voltage signal on the inputs must be referenced to a common mode, for example, agnd. the maximum common-mode signal is 100 mv, as shown in figure 24 . table 5. gain selection for channel 1 g1 g0 gain maximum differential signal (mv) 0 0 1 470 0 1 2 235 1 0 8 60 1 1 16 30
ade7755 rev. a | page 14 of 20 channel 2 (voltage channel) the output of the line voltage transducer is connected to the ade7755 at this analog input. channel 2 is a fully differential voltage input. the maximum peak differential signal on channel 2 is 660 mv. figure 25 illustrates the maximum signal levels that can be connected to channel 2 of the ade7755. +660m v ? 660m v v cm v 2 differential input 660mv max peak common-mode 100mv max v2p v2n v2 v cm agnd 02896-025 figure 25. maximum signal levels, channel 2 channel 2 must be driven from a common-mode voltage, that is, the differential voltage signal on the input must be referenced to a common mode (usually agnd). the analog inputs of the ade7755 can be driven with common-mode voltages of up to 100 mv with respect to agnd. however, best results are achieved using a common mode equal to agnd. typical connection diagrams figure 26 shows a typical connection diagram for channel 1. a current transformer (ct) is the current transducer selected for this example. note that the common-mode voltage for channel 1 is agnd and is derived by center-tapping the burden resistor to agnd. this provides the complementary analog input signals for v1p and v1n. the ct turns ratio and burden resistor rb are selected to give a peak differential voltage of 470 mv/gain at maximum load. v1p agnd 470mv gain rb rf rf ct neutral phase ip v1n cf cf 0 2896-026 figure 26. typical connection for channel 1 figure 27 shows two typical connections for channel 2. the first option uses a potential transformer (pt) to provide complete isolation from the power line. in the second option, the ade7755 is biased around the neutral wire, and a resistor divider provides a voltage signal that is proportional to the line voltage. adjusting the ratio of ra, rb, and vr is also a convenient way of carrying out a gain calibration on the meter. 660mv ra 1 rb 1 vr 1 v2p agnd rf rf pt neutral phase v2n cf cf 660mv v2p rf neutral phase v2n cf cf 1 ra >> rb + vr rb + vr = rf 02896-027 figure 27. typical connections for channel 2 power supply monitor the ade7755 contains an on-chip power supply monitor. the analog supply (av dd ) is continuously monitored by the ade7755. if the supply is less than 4 v 5%, the ade7755 resets. this is useful to ensure correct device startup at power-up and power- down. the power supply monitor has built-in hysteresis and filtering. these features give a high degree of immunity to false triggering due to noisy supplies. in figure 28 , the trigger level is nominally set at 4 v. the tolerance on this trigger level is about 5%. the power supply and decoupling for the part should be such that the ripple at av dd does not exceed 5 v 5%, as specified for normal operation. av dd 5v 4v 0v time reset active reset interna l reset 0 2896-028 figure 28. on-chip power supply monitor
ade7755 rev. a | page 15 of 20 hpf and offset effects figure 29 shows the effect of offsets on the active power calculation. an offset on channel 1 and channel 2 contributes a dc component after multiplication. because the dc component is extracted by the lpf, it accumulates as active power. if not properly filtered, dc offsets introduce error to the energy accumulation. this problem is easily avoided by enabling the hpf (that is, the ac/ dc pin is set to logic high) in channel 1. by removing the offset from at least one channel, no error component can be generated at dc by the multiplication. error terms at cos(t) are removed by the lpf and the digital-to-frequency conversion (see the section). digital-to- frequency conversion {v cos( t ) + v os } {i cos( t ) + i os } = )2cos( 2 )cos( )cos( 2 t iv tvitiviv iv os ososos ? +?+?++ dc component (including error term) is extracted by the lpf for active power calculation i os v v os i v os i os v i 2 0 & 2 & frequency (rad/s) 02896-029 figure 29. effect of channel offset on the active power calculation the hpf in channel 1 has an associated phase response that is compensated for on chip. the phase compensation is activated when the hpf is enabled and is disabled when the hpf is not activated. figure 30 and figure 31 show the phase error between channels with the compensation network activated. the ade7755 is phase compensated up to 1 khz, as shown. this ensures correct active harmonic power calculation even at low power factors. frequency (hz) 0 100 200 300 400 500 600 700 800 900 1000 phase (degrees) ?0.05 ?0.10 0 0.05 0.10 0.15 0.20 0.25 0.30 0 2896-030 figure 30. phase error between channels (0 hz to 1 khz) frequency (hz) 40 45 50 55 60 65 70 phase (degrees) ?0.05 ?0.10 0 0.05 0.10 0.15 0.20 0.25 0.30 0 2896-031 figure 31. phase error between channels (40 hz to 70 hz) digital-to-freuec coersio the digital output of the low-pass filter after multiplication contains the active power information. however, because this lpf is not an ideal brick-wall filter implementation, the output signal also contains attenuated components at the line frequency and its harmonics, that is, cos(ht) where h = 1, 2, 3, and so on. the magnitude response of the filter is given by )hz8.9/(1 1 )( f fh + = (4) for a line frequency of 50 hz, the filter gives an attenuation of the 2 (100 hz) component of approximately ?22 db. the dominating harmonic is at twice the line frequency, that is, cos(2 t), which is due to the instantaneous power signal. figure 32 shows the instantaneous active power signal at the output of the lpf, which still contains a significant amount of instantaneous power information, that is, cos(2 t). this signal is then passed to the digital-to-frequency converter where it is integrated (accumulated) over time to produce an output frequency. this accumulation of the signal suppresses or averages out any non-dc components in the instantaneous active power signal. the average value of a sinusoidal signal is 0. therefore, the frequency generated by the ade7755 is proportional to the average active power. figure 32 shows the digital-to-frequency conversion for steady load conditions, that is, constant voltage and current.
ade7755 rev. a | page 16 of 20 f1 f2 digital-to- frequency cf digital-to- frequency multiplier f1 time f out time frequency frequency v i 0 frequency (rad/s) 2 cos(2 t) attenuated by lpf vi 2 lpf to extract real power (dc term) instantaneous active power signal (frequency domain) lpf 02896-032 figure 32. active power-to-frequency conversion as can be seen in figure 32 , the frequency output cf varies over time, even under steady load conditions. this frequency variation is primarily due to the cos(2 t) component in the instantaneous active power signal. the output frequency on cf can be up to 2048 times higher than the frequency on f1 and f2. this higher output frequency is generated by accumulating the instantaneous active power signal over a much shorter time while converting it to a frequency. this shorter accumulation period means less averaging of the cos(2 t) component. consequently, some of this instantaneous power signal passes through the digital-to- frequency conversion, which is not a problem in the application. when cf is used for calibration purposes, the frequency should be averaged by the frequency counter. this averaging operation removes any ripple. if cf is measuring energy, for example, in a microprocessor-based application, the cf output should also be averaged to calculate power. because the outputs, f1 and f2, operate at a much lower frequency, more averaging of the instantaneous active power signal is carried out. the result is a greatly attenuated sinusoidal content and a virtually ripple-free frequency output. interfacing the ade7755 to a microcontroller for energy measurement the easiest way to interface the ade7755 to a microcontroller is to use the cf high frequency output with the output frequency scaling set to 2048 f1, f2. this is done by setting scf = 0 and s0 = s1 = 1 (see table 8 ). with full-scale ac signals on the analog inputs, the output frequency on cf is approximately 5.5 khz. figure 33 illustrates one scheme that can be used to digitize the output frequency and carry out the necessary averaging described in the digital-to-frequency conversion section. cf time 10% frequency ripple average frequency ade7755 1 revp must be used if the meter is bidirectional or direction of energy flow is needed counter up/down timer mcu cf revp 1 02896-033 figure 33. interfacing the ade7755 to an mcu as shown in figure 33 , the frequency output cf is connected to an mcu counter or port, which counts the number of pulses in a given integration time that is determined by an mcu internal timer. the average power proportional to the average frequency is given by time r counter power active average frequency average the energy consumed during an integration period is given by counter time time counter time power average energy u u for the purpose of calibration, this integration time can be 10 seconds to 20 seconds to accumulate enough pulses to ensure correct averaging of the frequency. in normal operation, the integration time can be reduced to 1 second or 2 seconds depending, for example, on the required update rate of a display. with shorter integration times on the mcu, the amount of energy in each update may still have some small amount of ripple, even under steady load conditions. however, over a minute or more, the measured energy has no ripple. power measurement considerations calculating and displaying power information always has some associated ripple that depends on the integration period used in the mcu to determine average power and also the load. for example, at light loads, the output frequency can be 10 hz. with an integration period of 2 seconds, only about 20 pulses are counted. the possibility of missing one pulse always exists because the ade7755 output frequency is running asynchronously to the mcu timer. this possibility results in a 1-in-20 (or 5%) error in the power measurement.
ade7755 rev. a | page 17 of 20 if the on-chip reference is used, actual output frequencies may vary from device to device due to a reference tolerance of 8%. transfer function frequency outputs f1 and f2 example 2 the ade7755 calculates the product of two voltage signals (on channel 1 and channel 2) and then low-pass filters this product to extract active power information. this active power information is then converted to a frequency. the frequency information is output on f1 and f2 in the form of active low pulses. the pulse rate at these outputs is relatively low, for example, 0.34 hz maximum for ac signals with s0 = s1 = 0 (see table 7 ). this means that the frequency at these outputs is generated from active power information accumulated over a relatively long time. the result is an output frequency that is proportional to the average active power. the averaging of the active power signal is implicit to the digital-to-frequency conversion. the output frequency or pulse rate is related to the input voltage signals by the following equation: in this example, with ac voltages of 470 mv peak applied to v1 and 660 mv peak applied to v2, the expected output frequency is calculated as follows: 34.0 5.222 7.1166.047.006.8 2 = = freq where: gain = 1, g0 = g1 = 0. f i = f 1 = 1.7 hz, s0 = s1 = 0. v1 = rms of 470 mv peak ac = 0.47/2 v. v2 = rms of 660 mv peak ac = 0.66/2 v. v ref = 2.5 v (nominal reference value). if the on-chip reference is used, actual output frequencies may vary from device to device due to a reference tolerance of 8%. 2 06.8 ref i v fgainv2v1 freq = as can be seen from these two example calculations, the maximum output frequency for ac inputs is always half that for dc input signals. table 7 shows a complete listing of all the maximum output frequencies. where: freq = output frequency on f1 and f2 (hz). v1 = differential rms voltage signal on channel 1 (volts). v2 = differential rms voltage signal on channel 2 (volts). gain = 1, 2, 8, or 16, depending on the pga gain selection made using logic inputs g0 and g1. v ref = the reference voltage (2.5 v 8%) (volts). f i = one of the four possible frequencies (f 1 , f 2 , f 3 , or f 4 ) selected by using the logic inputs s0 and s1, see tabl e 6 . table 7. maximum output frequency on f1 and f2 s1 s0 maximum frequency for dc inputs (hz) maximum frequency for ac inputs (hz) 0 0 0.68 0.34 0 1 1.36 0.68 1 0 2.72 1.36 1 1 5.44 2.72 table 6. f 1 , f 2 , f 3 , and f 4 frequency selection s1 s0 f 1 , f 2 , f 3 , and f 4 (hz) xtal/clkin 1 frequency output cf 0 0 f 1 = 1.7 3.579 mhz/2 21 the pulse output cf is intended for use during calibration. the output pulse rate on cf can be up to 2048 times the pulse rate on f1 and f2. the lower the f i frequency selected (i = 1, 2, 3, or 4), the higher the cf scaling (except for the high frequency mode scf = 0, s1 = s0 = 1). table 8 shows how the two frequencies are related, depending on the state of the logic inputs, s0, s1, and scf. because of its relatively high pulse rate, the frequency at cf is proportional to the instantaneous active power. as is the case with f1 and f2, the frequency is derived from the output of the low-pass filter after multiplication. however, because the output frequency is high, this active power information is accumulated over a much shorter time. therefore, less averaging is carried out in the digital-to-frequency conversion. with much less averaging of the active power signal, the cf output is much more responsive to power fluctuations (see the signal processing block diagram in figure 22 ). 0 1 f 2 = 3.4 3.579 mhz/2 20 1 0 f 3 = 6.8 3.579 mhz/2 19 1 1 f 4 = 13.6 3.579 mhz/2 18 1 f 1 , f 2 , f 3 , or f 4 is a binary fraction of the master clock and, therefore, varies if the specified clkin frequency is altered. example 1 if full-scale differential dc voltages of +470 mv and ?660 mv are applied to v1 and v2, respectively (470 mv is the maximum differential voltage that can be connected to channel 1, and 660 mv is the maximum differential voltage that can be connected to channel 2), the expected output frequency is calculated as follows: 2 06.8 ref i v fgainv2v1 freq = where: gain = 1, g0 = g1 = 0. f i = f 1 = 1.7 hz, s0 = s1 = 0. v1 = +470 mv dc = 0.47 v (rms of dc = dc). v2 = ?660 mv dc = 0.66 v (rms of dc = |dc|). v ref = 2.5 v (nominal reference value).
ade7755 rev. a | page 18 of 20 table 8. maximum output frequency on cf scf s1 s0 f 1 , f 2 , f 3 , and f 4 (hz) cf maximum for ac signals 1 0 0 f 1 = 1.7 128 f1, f2 = 43.52 hz 0 0 0 f 1 = 1.7 64 f1, f2 = 21.76 hz 1 0 1 f 2 = 3.4 64 f1, f2 = 43.52 hz 0 0 1 f 2 = 3.4 32 f1, f2 = 21.76 hz 1 1 0 f 3 = 6.8 32 f1, f2 = 43.52 hz 0 1 0 f 3 = 6.8 16 f1, f2 = 21.76 hz 1 1 1 f 4 = 13.6 16 f1, f2 = 43.52 hz 0 1 1 f 4 = 13.6 2048 f1, f2 = 5.57 khz selecting a frequency for an energy meter application as shown in table 6 , the user can select one of four frequencies. this frequency selection determines the maximum frequency on f1 and f2. these outputs are intended to be used to drive the energy register (electromechanical or other). because only four different output frequencies can be selected, the available frequency selection has been optimized for a meter constant of 100 imp/kwh with a maximum current between 10 a and 120 a. table 9 shows the output frequency for several maximum currents (i max ) with a line voltage of 220 v. in all cases, the meter constant is 100 imp/kwh. table 9. f1 and f2 frequency at 100 imp/kwh i max (a) f1 and f2 (hz) 12.5 0.076 25 0.153 40 0.244 60 0.367 80 0.489 120 0.733 the f i frequencies (i = 1, 2, 3, or 4) allow complete coverage of this range of output frequencies on f1 and f2. when designing an energy meter, the nominal design voltage on channel 2 (voltage) should be set to half scale to allow for calibration of the meter constant. the current channel should also be no more than half scale when the meter sees maximum load. this allows overcurrent signals and signals with high crest factors to be accommodated. table 10 shows the output frequency on f1 and f2 when both analog inputs are half scale. the frequencies listed in table 10 align well with those listed in table 9 for maximum load. table 10. f1 and f2 frequency with half-scale ac inputs s1 s0 f 1 , f 2 , f 3 , and f 4 (hz) f1 and f2 frequency on ch1 and ch2 half-scale ac inputs (hz) 0 0 f 1 = 1.7 0.085 0 1 f 2 = 3.4 0.17 1 0 f 3 = 6.8 0.34 1 1 f 4 = 13.6 0.68 when selecting a suitable f i frequency (i = 1, 2, 3, or 4) for a meter design, the frequency output at i max (maximum load) with a meter constant of 100 imp/kwh should be compared with column 4 of table 10 . the frequency that is closest in table 10 determines the best choice of f i frequency (i = 1, 2, 3, or 4). for example, if a meter with a maximum current of 25 a is being designed, the output frequency on f1 and f2 with a meter constant of 100 imp/kwh is 0.153 hz at 25 a and 220 v (from table 9 ). table 10 , the closest frequency to 0.153 hz in column 4, is 0.17 hz. therefore, f 2 (3.4 hz, see table 6 ) is selected for this design. frequency outputs figure 2 shows a timing diagram for the various frequency outputs. the f1 and f2 outputs are the low frequency outputs that can be used to directly drive a stepper motor or electro- mechanical impulse counter. the f1 and f2 outputs provide two alternating low going pulses. the pulse width (t 1 ) is set at 275 ms, and the time between the falling edges of f1 and f2 (t 3 ) is approximately half the period of f1 (t 2 ). if, however, the period of f1 and f2 falls below 550 ms (1.81 hz), the pulse width of f1 and f2 is set to half of their period. the maximum output frequencies for f1 and f2 are shown in table 7 . the high frequency cf output is intended to be used for communications and calibration purposes. cf produces a 90 ms wide active high pulse (t 4 ) at a frequency proportional to active power. the cf output frequencies are listed in table 8 . as in the case of f1 and f2, if the period of cf (t 5 ) falls below 180 ms, the cf pulse width is set to half the period. for example, if the cf frequency is 20 hz, the cf pulse width is 25 ms. when the high frequency mode is selected (that is, scf = 0, s1 = s0 = 1), the cf pulse width is fixed at 18 s. therefore, t 4 is always 18 s, regardless of the output frequency on cf.
ade7755 rev. a | page 19 of 20 no load threshold the ade7755 also includes a no load threshold and start-up current feature that eliminates any creep effects in the meter. the ade7755 is designed to issue a minimum output frequency in all modes except when scf = 0 and s1 = s0 = 1. the no load detection threshold is disabled in this output mode to accommodate specialized application of the ade7755. any load generating a frequency lower than this minimum frequency will not cause a pulse to be issued on f1, f2, or cf. the minimum output frequency is given as 0.0014% of the full-scale output frequency for each of the f i frequencies (i = 1, 2, 3, or 4), see table 6 . for example, in an energy meter with a meter constant of 100 imp/kwh on f1 and f2 using f 2 (3.4 hz), the maximum output frequency at f1 or f2 is 0.0014% of 3.4 hz or 4.76 10 ?5 hz. this is 3.05 10 ?3 hz at cf (64 f1 hz). in this example, the no load threshold is equivalent to 1.7 w of the load or a start-up current of 8 ma at 220 v. iec 1036 states that the meter must start up with a load current equal to or less than 0.4% ib. for a 5 a (ib) meter, 0.4% ib is equivalent to 20 ma. the start-up current of this design therefore satisfies the iec requirement. as illustrated in this example, the choice of f i frequency (i = 1, 2, 3, or 4) and the ratio of the stepper motor display determine the start-up current.
ade7755 rev. a | page 20 of 20 outline dimensions compliant to jedec standards mo-150-ag 060106-a 24 13 12 1 8.50 8.20 7.90 8.20 7.80 7.40 5.60 5.30 5.00 seating plane 0.05 min 0.65 bsc 2.00 max 0.38 0.22 coplanarity 0.10 1.85 1.75 1.65 0.25 0.09 0.95 0.75 0.55 8 4 0 figure 34. 24-lead shrink small outline package [ssop] (rs-24) dimensions shown in millimeters ordering guide model temperature range package description package option ADE7755ARSZ 1 ?40c to +85c 24-lead shrink small outline package [ssop] rs-24 ade7755arsrlz 1 ?40c to +85c 24-lead shrink small outline package [ssop], 13 tape and reel rs-24 eval-ade7755ebz 1 ?40c to +85c evaluation board 1 z = rohs compliant part. ?2002C2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d02896-0-8/09(a)

▲Up To Search▲

Price & Availability of ADE7755ARSZ

	To Download ADE7755ARSZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .